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this is information on a product in full production. october 2012 doc id 022098 rev 3 1/43 43 l7986ta 3 a step-down switching regulator datasheet ? production data features 3 a dc output current 4.5 v to 38 v input voltage output voltage adjustable from 0.6 v 250 khz switching frequency, programmable up to 1 mhz internal soft-start and enable low dropout operation: 100% duty cycle voltage feed-forward zero load current operation overcurrent and thermal protection hsop8 package guarantee overtemperature range (-40 c to 125 c) applications automotive: ? car audio, car infotainment industrial: ? pld, pla, fpga, chargers networking: xdsl, modems, dc-dc modules computer: ? optical storage, hard disk drive, printers led driving description the l7986ta is a step-down switching regulator with 3.7 a (min.) current limited embedded power mosfet, so it is able to deliver up to 3 a current to the load depending on the application conditions. the input voltage can range from 4.5 v to 38 v, while the output voltage can be set starting from 0.6 v to v in . requiring a minimum set of external components, the device includes an internal 250 khz switching frequency oscillator that can be externally adjusted up to 1 mhz. the hsop package with exposed pad allows the reduction of r thja down to 40 c/w. hsop8 exposed pad www.st.com
contents l7986ta 2/43 doc id 022098 rev 3 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.1 type iii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.2 type ii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
l7986ta contents doc id 022098 rev 3 3/43 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
pin settings l7986ta 4/43 doc id 022098 rev 3 1 pin settings 1.1 pin connection figure 1. pin connection (top view) 1.2 pin description table 1. pin description n. type description 1 out regulator output 2 synch master/slave synchronization. when it is left floating, a signal with a phase shift of half a period, with respect to the power turn-on, is present at the pin. when connected to an external signal at a frequency higher than the internal one, the device is synchronized by the external signal, with zero phase shift. connecting together the synch pin of two devices, the one with a higher frequency works as master and the other as slave; so the two powers turn-ons have a phase shift of half a period. 3en a logical signal (active high) enables the device. with en higher than 1.2 v the device is on and with en lower than 0.3 v the device is off. 4 comp error amplifier output to be used for loop frequency compensation. 5fb feedback input. by connecting the output voltage directly to this pin the output voltage is regulated at 0.6 v. to have higher regulated voltages an external resistor divider is required from v out to the fb pin. 6f sw the switching frequency can be increased connecting an external resistor from the fsw pin and ground. if this pin is left floating, the device works at its free-running frequency of 250 khz. 7 gnd ground 8v cc unregulated dc input voltage.
l7986ta maximum ratings doc id 022098 rev 3 5/43 2 maximum ratings 3 thermal data table 2. absolute maximum ratings symbol parameter value unit vcc input voltage 45 v out output dc voltage -0.3 to v cc f sw , comp, synch analog pin -0.3 to 4 en enable pin -0.3 to v cc fb feedback voltage -0.3 to 1.5 p tot power dissipation at t a < 60 c hsop 2 w t j junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction-ambient (1) 1. package mounted on demonstration board. hsop8 40 c/w
electrical characteristics l7986ta 6/43 doc id 022098 rev 3 4 electrical characteristics t j =-40 c to 125 c, v cc =12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition values unit min. typ. max. v cc operating input voltage range 4.5 38 v v ccon tu r n - o n v cc threshold 4.5 v cchys v cc uvlo hysteresis 0.1 0.4 r dson mosfet on resistance 200 400 m i lim maximum limiting current t j =25 c 3.7 4.2 4.7 a 3.5 4.7 oscillator f sw switching frequency 210 250 275 khz v fsw fsw pin voltage 1.254 v dduty cycle 0 100% f adj adjustable switching frequency r fsw =33 k 1000 khz dynamic characteristics v fb feedback voltage 4.5 v l7986ta electrical characteristics doc id 022098 rev 3 7/43 error amplifier v ch high level output voltage v fb <0.6 v 3 v v cl low level output voltage v fb >0.6 v 0.1 i o source source comp pin v fb =0.5 v, v comp =1 v 19 ma i o sink sink comp pin v fb =0.7 v, v comp =1 v 30 ma g v open-loop voltage gain (1) 100 db synchronization function v s_in,hi high input voltage 2 3.3 v v s_in,lo low input voltage 1 t s_in_pw input pulse width v s_in,hi =3 v, v s_in,lo =0 v 100 ns v s_in,hi =2 v, v s_in,lo =1 v 300 i synch,lo slave sink current v synch =2.9 v 0.7 1 ma v s_out,hi master output amplitude i source =4.5 ma 2 v t s_out_pw output pulse width synch floating 110 ns protection t shdn thermal shutdown 150 c hysteresis 30 1. guaranteed by design. table 4. electrical characteristics (continued) symbol parameter test condition values unit min. typ. max.
functional description l7986ta 8/43 doc id 022098 rev 3 5 functional description the l7986ta is based on a ?voltage mode?, constant frequency control. the output voltage v out is sensed by the feedback pin (fb) compared to an internal reference (0.6 v) providing an error signal that, compared to a fixed frequency sawtooth, controls the on- and off-time of the power switch. the main internal blocks are shown in the block diagram in figure 2 . they are: a fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. its switching frequency can be adjusted by an external resistor. the voltage and frequency feed-forward are implemented. the soft-start circuitry to limit inrush current during the startup phase. the voltage mode error amplifier. the pulse width modulator and the relative logic circuitry necessary to drive the internal power switch. the high-side driver for embedded p-channel power mosfet switch. the peak current limit sensing block, to handle overload and short-circuit conditions. a voltage regulator and internal reference. it supplies internal circuitry and provides a fixed internal reference. a voltage monitor circuitry (uvlo) that checks the input and internal voltages. a thermal shutdown block, to prevent thermal runaway. figure 2. block diagram peak current limit oscillator s r q thermal shutdown soft- start en trimming uvlo 0.6v regulator & bandgap 1.254v 3.3v synch & phase shift en fb comp fsw gnd synch out vcc driver e/a pwm peak current limit oscillator s r q thermal shutdown soft- start en trimming uvlo uvlo 0.6v regulator & bandgap regulator & bandgap 1.254v 3.3v synch & phase shift en fb comp fsw gnd synch out vcc driver e/a pwm
l7986ta functional description doc id 022098 rev 3 9/43 5.1 oscillator and synchronization figure 3 shows the block diagram of the oscillator circuit. the internal oscillator provides a constant frequency clock. its frequency depends on the resistor externally connect to the fsw pin. if the fsw pin is left floating, the frequency is 250 khz; it can be increased as shown in figure 5 by an external resistor connected to ground. to improve the line transient performance, keeping the pwm gain constant versus the input voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth according to the input voltage change (see figure 4 .a). the slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. in this way a frequency feed-forward is implemented ( figure 4 .b) in order to keep the pwm gain constant versus the switching frequency (see section 6.4 for pwm gain expression). on the synch pin the synchronization signal is generated. this signal has a phase shift of 180 with respect to the clock. this delay is useful when two devices are synchronized connecting the synch pins together. when synch pins are connected, the device with a higher oscillator frequency works as master, so the slave device switches at the frequency of the master but with a delay of half a period. this minimizes the rms current flowing through the input capacitor (see the l5988d datasheet). figure 3. oscillator circuit block diagram the device can be synchronized to work at a higher frequency feeding an external clock signal. the synchronization changes the sawtooth amplitude, changing the pwm gain ( figure 4 .c). this change must be taken into account when the loop stability is studied. to minimize the change of the pwm gain, the free-running frequency should be set (with a resistor on the fsw pin) only slightly lower than the external clock frequency. this pre- adjusting of the frequency changes the sawtooth slope in order to render the truncation of sawtooth negligible, due to the external synchronization. clock generator ramp generator fsw sawtooth clock synchronization synch clock generator ramp generator fsw sawtooth clock clock synchronization synch
functional description l7986ta 10/43 doc id 022098 rev 3 figure 4. sawtooth: voltage and frequency feed-forward; external synchronization figure 5. oscillator frequency vs. fsw pin resistor
l7986ta functional description doc id 022098 rev 3 11/43 5.2 soft-start the soft-start is essential to assure correct and safe startup of the step-down converter. it avoids inrush current surge and makes the output voltage increase monothonically. the soft-start is performed by a staircase ramp on the non-inverting input (v ref ) of the error amplifier. so the output voltage slew rate is: equation 1 where sr vref is the slew rate of the non-inverting input, while r1and r2 is the resistor divider to regulate the output voltage (see figure 6 ). the soft-start staircase consists of 64 steps of 9.5 mv each, from 0 v to 0.6 v. the time base of one step is of 32 clock cycles. so the soft-start time and then the output voltage slew rate depend on the switching frequency. figure 6. soft-start scheme. soft-start time results: equation 2 for example, with a switching frequency of 250 khz the ss time is 8 ms. sr out sr vref 1 r1 r2 ------- - + ?? ?? ? = ss time 32 64 ? fsw -------------------- =
functional description l7986ta 12/43 doc id 022098 rev 3 5.3 error amplifier and compensation the error amplifier (e/a) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. its non-inverting input is internally connected to a 0.6 v voltage reference, while its inverting input (fb) and output (comp) are externally available for feedback and frequency compensation. in this device the error amplifier is a voltage mode operational amplifier, therefore, with high dc gain and low output impedance. the uncompensated error amplifier characteristics are the following: in continuous conduction mode (ccm), the transfer function of the power section has two poles due to the lc filter and one zero due to the esr of the output capacitor. different kinds of compensation networks can be used depending on the esr value of the output capacitor. if the zero introduced by the output capacitor helps to compensate the double pole of the lc filter, a type ii compensation network can be used. otherwise, a type iii compensation network must be used (see section 6.4 for details of the compensation network selection). anyway, the methodology to compensate the loop is to introduce zeroes to obtain a safe phase margin. table 5. uncompensated error amplifier characteristics parameter value low frequency gain 100 db gbwp 4.5 mhz slew rate 7 v/ s output voltage swing 0 to 3.3 v maximum source/sink current 17 ma/25 ma
l7986ta functional description doc id 022098 rev 3 13/43 5.4 overcurrent protection the l7986ta implements overcurrent protection by sensing current flowing through the power mosfet. due to the noise created by the switching activity of the power mosfet, the current sensing is disabled during the initial phase of the conduction time. this avoids an erroneous detection of a fault condition. this interval is generally known as ?masking time? or ?blanking time?. the masking time is about 200 ns. if the overcurrent limit is reached, the power mosfet is turned off implementing pulse-by- pulse overcurrent protection. in the overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. if, at the end of the ?masking time?, the current is higher than the overcurrent threshold, the power mosfet is turned off and one pulse is skipped. if, at the following switching on, when the ?masking time? ends, the current is still higher than the overcurrent threshold, the device skips two pulses. this mechanism is repeated and the device can skip up to seven pulses. while, if at the end of the ?masking time?, the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit (see figure 7 ). so, the overcurrent/short-circuit protection acts by switching off the power mosfet and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit. this kind of overcurrent protection is effective if the output current is limited. to prevent the current from diverging, the current ripple in the inductor during the on-time must not be higher than the current ripple during the off-time. that is: equation 3 if the output voltage is shorted, v out ? 0, i out =i lim , d/f sw =t on_min , (1-d)/f sw ? 1/f sw . so, from equation 3 , the maximum switching frequency that guarantees to limit the current results: equation 4 with r dson =300 m , drc=0.08 , the worst condition is with v in =38 v, i lim =3.7 a; the maximum frequency to keep the output current limited during the short-circuit results 88 khz. the pulse-by-pulse mechanism, which reduces the switching frequency down to one eighth the maximum f sw , adjusted by the fsw pin, that assures a full effective output current limitation, is 88 khz*8 = 706 khz. v in v ? out r dson i out ? dcr i out ? ? ? lf sw ? ------------------------------------------------------------------------------------------------------------------------ - d ? v out v f r dson i out ? dcr i out ? ++ + lf sw ? ----------------------------------------------------------------------------------------------------------------------- 1d ? () ? = f sw * v f dcr i ? + lim () v in r dson dcr + () i lim ? ? () ------------------------------------------------------------------------------------- 1 t on_min ------------------------ - ? =
functional description l7986ta 14/43 doc id 022098 rev 3 if, with v in =38 v, the switching frequency is set higher than 706 khz, during short-circuit condition the system finds a different equilibrium with higher current. for example, with f sw =800 khz and the output shorted to ground, the output current is limited around: equation 5 where f sw * is 800 khz divided by eight. figure 7. overcurrent protection 5.5 enable function the enable feature allows to put the device into standby mode. with the en pin lower than 0.3 v the device is disabled and the power consumption is reduced to less than 30 a. with the en pin lower than 1.2 v, the device is enabled. if the en pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v cc compatible. 5.6 hysteretic thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 c. once the junction temperature returns to about 120 c, the device restarts in normal operation. the sensing element is very close to the pdmos area, so ensuring an accurate and fast temperature detection. i out v in f sw * ? v f t on_min ? ? drc t on_min ? () r dson dcr + () f sw * ? + --------------------------------------------------------------------------------------------------------------------------- 4.2a ==
l7986ta application information doc id 022098 rev 3 15/43 6 application information 6.1 input capacitor selection the capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum rms input current required by the device. the input capacitor is subject to a pulsed current, the rms value of which is dissipated over its esr, affecting the overall system efficiency. so, the input capacitor must have an rms current rating higher than the maximum rms input current and an esr value compliant with the expected efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 6 where io is the maximum dc output current, d is the duty cycle, is the efficiency. considering =1 , this function has a maximum at d=0.5 and it is equal to io/2. in a specific application, the range of possible duty cycles must be considered in order to find out the maximum rms input current. the maximum and minimum duty cycles can be calculated as: equation 7 and equation 8 where v f is the forward voltage on the freewheeling diode and v sw is the voltage drop across the internal pdmos. the peak-to-peak voltage across the input capacitor can be calculated as: equation 9 where esr is the equivalent series resistance of the capacitor. i rms i o d 2d 2 ? ----------------- - ? d 2 2 ------ - + ? = d max v out v f + v inmin v sw ? --------------------------------------- = d min v out v f + v inmax v sw ? ----------------------------------------- = v pp i o c in f sw ? ----------------------------- - 1 d --- - ? ?? ?? d d --- - 1d ? () ? + ? esr i o ? + ? =
application information l7986ta 16/43 doc id 022098 rev 3 given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input rms current than electrolytic/tantalum types. in this case the equation of c in as a function of the target v pp can be written as follows: equation 10 neglecting the small esr of ceramic capacitors. considering =1, this function has its maximum in d=0.5, therefore, given the maximum peak-to-peak input voltage (v pp_max ), the minimum input capacitor (c in_min ) value is: equation 11 typically c in is dimensioned to keep the maximum peak-to-peak voltage in the order of 1% of v inmax in tab le 6 some multi-layer ceramic capacitors suitable for this device are reported. a ceramic bypass capacitor, as close to the vcc and gnd pins as possible, so that additional parasitic esr and esl are minimized, is suggested in order to prevent instability on the output voltage due to noise. the value of the bypass capacitor can go from 100 nf to 1 f. 6.2 inductor selection the inductance value fixes the current ripple flowing through the output capacitor. so the minimum inductance value, in order to have the expected current ripple, must be selected. the rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. in the continuous current mode (ccm), the inductance value can be calculated by the following equation: equation 12 table 6. input mlcc capacitors manufacture series cap value ( f) rated voltage (v) taiyo yuden UMK325BJ106MM-T 10 50 gmk325bj106mn-t 10 35 murata grm32er71h475k 4.7 50 c in i o v pp f sw ? ------------------------------- 1 d --- - ? ?? ?? d d --- - 1d ? () ? + ? ? = c in_min i o 2v pp_max f sw ?? -------------------------------------------------------- - = i l v in v out ? l ------------------------------- - t on ? v out v f + l ----------------------------- t off ? ==
l7986ta application information doc id 022098 rev 3 17/43 where t on is the conduction time of the internal high-side switch and t off is the conduction time of the external diode (in ccm, f sw =1/(t on + t off )). the maximum current ripple, at fixed v out , is obtained at maximum t off which is at minimum duty cycle (see section 6.1 to calculate minimum duty). so, by fixing i l =20% to 30% of the maximum output current, the minimum inductance value can be calculated: equation 13 where f sw is the switching frequency, 1/(t on + t off ). for example, for v out =5 v, v in =24 v, i o =3 a and f sw =250 khz, the minimum inductance value to have i l =30% of i o is about 18 h. the peak current through the inductor is given by: equation 14 so, if the inductor value decreases, then the peak current (that must be lower than the minimum current limit of the device) increases. according to the maximum dc output current for this product family (3 a), the higher the inductor value, the higher the average output current that can be delivered, without triggering the overcurrent protection. in ta b l e 7 some inductor part numbers are listed. 6.3 output capacitor selection the current in the capacitor has a triangular waveform which generates a voltage ripple across it. this ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its esr). so the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. the amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. table 7. inductors manufacturer series inductor value ( h) saturation current (a) coilcraft mss1038 3.8 to 10 3.9 to 6.5 mss1048 12 to 22 3.84 to 5.34 wurth pd type l 8.2 to 15 3.75 to 6.25 pd type m 2.2 to 4.7 4 to 6 sumida cdrh6d226/hp 1.5 to 3.3 3.6 to 5.2 cdr10d48mn 6.6 to 12 4.1 to 5.7 l min v out v f + i max ----------------------------- 1d min ? f sw ----------------------- - ? = i lpk , i o i l 2 -------- + =
application information l7986ta 18/43 doc id 022098 rev 3 equation 15 usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (mlcc) with very low esr value. the output capacitor is important also for loop stability: it fixes the double lc filter pole and the zero due to its esr. section 6.4 illustrates how to consider its effect in the system stability. for example, with v out =5 v, v in =24 v, i l =0.9 a (resulting from the inductor value), in order to have a v out =0.01v out , if the multi-layer ceramic capacitors are adopted, 10 f are needed and the esr effect on the output voltage ripple can be neglected. in the case of non-negligible esr (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its esr value. so, in case of 330 f with esr=30 m , the resistive component of the drop dominates and the voltage ripple is 28 mv . the output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. when the load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. so, if the high slew rate load transient is required by the application, the output capacitor and system bandwidth must be chosen in order to sustain the load transient. in ta b l e 8 some capacitor series are listed. 6.4 compensation network the compensation network must assure stability and good dynamic performance. the loop of the l7986ta is based on the voltage mode control. the error amplifier is a voltage operational amplifier with high bandwidth. so, by selecting the compensation network the e/a is considered as ideal, that is, its bandwidth is much larger than the system one. the transfer functions of the pwm modulator and the output lc filter are studied (see figure 9 ). the transfer function of the pwm modulator, from the error amplifier output (comp pin) to the out pin, results: table 8. output capacitors manufacturer series cap value ( f) rated voltage (v) esr (m ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 v out esr i max ? i max 8c out f sw ?? -------------------------------------------- - + =
l7986ta application information doc id 022098 rev 3 19/43 equation 16 where v s is the sawtooth amplitude. as seen in section 5.1 , the voltage feed-forward generates a sawtooth amplitude directly proportional to the input voltage, that is: equation 17 in this way the pwm modulator gain results constant and equal to: equation 18 the synchronization of the device with an external clock provided trough the synch pin can modify the pwm modulator gain (see section 5.1 to understand how this gain changes and how to keep it constant in spite of the external synchronization). figure 8. the error amplifier, the pwm modulator, and the lc output filter the transfer function on the lc filter is given by: equation 19 where: g pw0 v in v s --------- = v s kv in ? = g pw0 v in v s --------- 1 k --- - 18 === fb comp v ref e/a pwm v s out v cc c out esr l g pw0 g lc fb comp v ref e/a pwm v s out v cc c out esr l g pw0 g lc g lc s () 1 s 2 f zesr ? ------------------------------ + 1 s 2 qf ? lc ? ---------------------------------- - s 2 f lc ? ---------------------- - ?? ?? 2 ++ ----------------------------------------------------------------------------------- =
application information l7986ta 20/43 doc id 022098 rev 3 equation 20 equation 21 as seen in section 5.3 , two different kinds of network can compensate the loop. in the following two paragraphs the guidelines to select the type ii and type iii compensation network are illustrated. 6.4.1 type iii compensation network the methodology to stabilize the loop consists of placing two zeroes to compensate the effect of the lc double pole, therefore increasing phase margin; then, to place one pole in the origin to minimize the dc error on regulated output voltage; and finally, to place other poles far from the zero db frequency. if the equivalent series resistance (esr) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 ? esr ? cout<1/bw), the type iii compensation network is needed. multi-layer ceramic capacitors (mlcc) have very low esr (<1 m ), with very high frequency zero, so a type iii network is adopted to compensate the loop. in figure 9 the type iii compensation network is shown. this network introduces two zeroes (f z1 , f z2 ) and three poles (f p0 , f p1 , f p2 ). they are expressed as: equation 22 equation 23 f lc 1 2 lc out ? 1 esr r out --------------- - + ?? ---------------------------------------------------------------------------------- - = f zesr 1 2 esr c out ?? -------------------------------------------------- - = , q r out lc out r out esr + () ?? ? lc out r out esr ?? + ------------------------------------------------------------------------------------------------------ - r out v out i out --------------- - = , = f z1 1 2 c 3 r 1 r 3 + () ?? ------------------------------------------------------ - = f z2 1 2 r 4 c 4 ?? ----------------------------------- - = , f p0 0 = f p1 1 2 r 3 c 3 ?? ------------------------------------ = f p2 1 2 r 4 c 4 c 5 ? c 4 c 5 + --------------------- - ?? --------------------------------------------------- = ,,
l7986ta application information doc id 022098 rev 3 21/43 figure 9. type iii compensation network in figure 10 the bode diagram of the pwm and lc filter transfer function (g pw0 g lc (f)) and the open-loop gain (g loop (f) = g pw0 g lc (f) g typeiii (f)) are drawn. figure 10. open-loop gain: module bode diagram the guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows: 1. choose a value for r 1 , usually between 1 k and 5 k . 2. choose a gain (r 4 /r 1 ) in order to have the required bandwidth (bw), that means: equation 24 where k is the feed-forward constant and 1/k is equal to 18. 3. calculate c 4 by placing the zero at 50% of the output filter double pole frequency (f lc ): r 4 bw f lc --------- - kr 1 ?? =
application information l7986ta 22/43 doc id 022098 rev 3 equation 25 4. calculate c 5 by placing the second pole at four times the system bandwidth (bw): equation 26 5. set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole: equation 27 the suggested maximum system bandwidth is equal to the switching frequency divided by 3.5 (f sw /3.5), anyway, lower than 100 khz if the f sw is set higher than 500 khz. for example, with v out =5 v, v in =24 v, i o =3 a, l=18 h, c out =22 f, and esr<1 m , the type iii compensation network is: equation 28 in figure 11 the module and phase of the open-loop gain is shown. the bandwidth is about 58 khz and the phase margin is 50 . c 4 1 r 4 f lc ?? --------------------------------- - = c 5 c 4 2 r 4 c 4 4bw ? 1 ? ??? ------------------------------------------------------------------------- = r 3 r 1 4bw ? f lc -------------------- 1 ? ----------------------------- - = c 3 1 2 r 3 4bw ??? ------------------------------------------------- = , 1 . = r 2 680 = r 3 200 = r 4 2k = c 3 3.3nf = c 4 22nf = c 5 220pf = ,,,, ,,
l7986ta application information doc id 022098 rev 3 23/43 figure 11. open-loop gain bode diagram with ceramic output capacitor
application information l7986ta 24/43 doc id 022098 rev 3 6.4.2 type ii comp ensation network if the equivalent series resistance (esr) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2 ? esr ? cout>1/bw), this zero helps stabilize the loop. electrolytic capacitors show non-negligible esr (>30 m ), so with this kind of output capacitor the type ii network combined with the zero of the esr allows to stabilize the loop. in figure 12 the type ii network is shown. figure 12. type ii compensation network the singularities of the network are: equation 29 in figure 13 the bode diagram of the pwm and lc filter transfer function (g pw0 g lc (f)) and the open-loop gain (g loop (f) = g pw0 g lc (f) g typeii (f)) are drawn. f z1 1 2 r 4 c 4 ?? ----------------------------------- - = f p0 0 = f p1 1 2 r 4 c 4 c 5 ? c 4 c 5 + --------------------- - ?? -------------------------------------------------- - = ,,
l7986ta application information doc id 022098 rev 3 25/43 figure 13. open-loop gain: module bode diagram the guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows: 1. choose a value for r 1 , usually between 1 k and 5 k , in order to have values of c4 and c5 not comparable with parasitic capacitance of the board. 2. choose a gain (r 4 /r 1 ) in order to have the required bandwidth (bw), that means: equation 30 where f esr is the esr zero: equation 31 and vs is the sawtooth amplitude. the voltage feed-forward keeps the ratio vs/vin constant. 3. calculate c 4 by placing the zero one decade below the output filter double pole: equation 32 r 4 f esr f lc ------------ - ?? ?? ?? 2 bw f esr ------------- v s v in --------- r 1 ??? = f esr 1 2 esr c out ?? -------------------------------------------------- - = c 4 10 2 r 4 f lc ?? ------------------------------------- =
application information l7986ta 26/43 doc id 022098 rev 3 4. then calculate c 3 in order to place the second pole at four times the system bandwidth (bw): equation 33 for example, with v out =5 v, v in =24 v, i o =3 a, l=18 h, c out =330 f, and esr=35 m , the type ii compensation network is: equation 34 in figure 14 the module and phase of the open-loop gain is shown. the bandwidth is about 21 khz and the phase margin is 45 . c 5 c 4 2 r 4 c 4 4bw ? 1 ? ??? ------------------------------------------------------------------------- = r 1 1.1k = r 2 150 = r 4 4.99k = c 4 82nf = c 5 68pf = ,, ,,
l7986ta application information doc id 022098 rev 3 27/43 figure 14. open-loop gain bode diagram with electrolytic/tantalum output capacitor 6.5 thermal considerations the thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 c. the three different sources of losses within the device are: a) conduction losses due to the non-negligible r dson of the power switch; these are equal to: equation 35 p on r dson i out () 2 d ?? =
application information l7986ta 28/43 doc id 022098 rev 3 where d is the duty cycle of the application and the maximum r dson overtemperature is 220 m . note that the duty cycle is theoretically given by the ratio between v out and v in , but actually it is quite higher in order to compensate the losses of the regulator. so the conduction losses increase compared with the ideal case. b) switching losses due to power mosfet turn-on and turn-off; these can be calculated as: equation 36 where t rise and t fall are the overlap times of the voltage across the power switch (v ds ) and the current flowing into it during turn-on and turn-off phases, as shown in figure 15 . t sw is the equivalent switching time. for this device the typical value for the equivalent switching time is 40 ns. c) quiescent current losses, calculated as: equation 37 where i q is the quiescent current (i q =2.4 ma). the junction temperature t j can be calculated as: equation 38 where t a is the ambient temperature and p tot is the sum of the power losses just seen. rth ja is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. for this device the path through the exposed pad is the one conducting the largest amount of heat. the rth ja measured on the demonstration board described in the following paragraph is about 40 c/w for the hsop package. p sw v in i out t rise t fall + () 2 --------------------------------------------- - fsw ?? ? v in i out t sw f sw ??? == p q v in i q ? = t j t a rth ja p tot ? + =
l7986ta application information doc id 022098 rev 3 29/43 figure 15. switching losses 6.6 layout considerations the pc board layout of the switching dc/dc regulator is very important to minimize the noise injected in high impedance nodes and interference generated by the high switching current loops. in a step-down converter the input loop (including the input capacitor, the power mosfet and the freewheeling diode) is the most critical one. this is due to the fact that the high value pulsed currents are flowing through it. in order to minimize the emi, this loop must be as short as possible. the feedback pin (fb) connection to the external resistor divider is a high impedance node, so the interferences can be minimized by placing the routing of the feedback node as far as possible from the high current paths. to reduce the pick-up noise, the resistor divider must be placed very close to the device. to filter the high frequency noise, a small bypass capacitor (220 nf - 1 f) can be added as close as possible to the input voltage pin of the device. thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion. in figure 16 a layout example is shown.
application information l7986ta 30/43 doc id 022098 rev 3 figure 16. layout example
l7986ta application information doc id 022098 rev 3 31/43 6.7 application circuit in figure 17 the demonstration board application circuit is shown. figure 17. demonstration board application circuit table 9. component list reference part number description manufacturer c1 UMK325BJ106MM-T 10 f, 50 v taiyo yuden c2 grm32er61e226ke15 22 f, 25 v murata c3 3.3 nf, 50 v c4 33 nf, 50 v c5 100 pf, 50 v c6 470 nf, 50 v r1 4.99 k , 1%, 0.1 w 0603 r2 1.1 k , 1%, 0.1 w 0603 r3 330 , 1%, 0.1 w 0603 r4 1.5 k , 1%, 0.1 w 0603 r5 180 k , 1%, 0.1 w 0603 d1 stps3l40 3 a dc, 40 v stmicroelectronics l1 mss1038-103nl 10 h, 30%, 3.9 a, dcr max =35 m coilcraft
application information l7986ta 32/43 doc id 022098 rev 3 figure 18. pcb layout: l7986ta (component side) figure 19. pcb layout: l7986ta (bottom side) figure 20. pcb layout: l7986ta (front side)
l7986ta application information doc id 022098 rev 3 33/43 figure 21. junction temperature vs. output current figure 22. junction temperature vs. output current v out =1.8v v out =3.3v v out =5v hsop vqfn v in =24v f sw =250khz t amb =25 c v out =1.8v v out =3.3v v out =5v hsop vqfn v in =12v f sw =250khz t amb =25 c figure 23. junction temperature vs. output current figure 24. efficiency vs. output current v out =1.2v v out =1.8v v out =3.3v hsop vqfn v in =5v f sw =250khz t amb =25 c 60 65 70 75 80 85 90 95 0.100 0.600 1.100 1.600 2.100 2.600 3.100 io [a] eff [%] vin=12v vin=18v vin=24v vo=5.0v fsw=250khz figure 25. efficiency vs. output current figure 26. efficiency vs. output current 50 55 60 65 70 75 80 85 90 95 0.100 0.600 1.100 1.600 2.100 2.600 3.100 io [a] eff [%] vin=5v vin=12v vin=24v vo=3.3v fsw=250khz 40 45 50 55 60 65 70 75 80 85 0.100 0.600 1.100 1.600 2.100 2.600 3.100 io [a] e ff [%] vin=5v vin=12v vin=24v vo=1.8v fsw=250khz
application information l7986ta 34/43 doc id 022098 rev 3 figure 27. load regulation figure 28. line regulation 3.305 3.310 3.315 3.320 3.325 3.330 3.335 3.340 3.345 3.350 0.00 0.50 1.00 1.50 2.00 2.50 3.00 v out [v] io [a] vin=5v vin=12v vin=24v 3.3200 3.3250 3.3300 3.3350 3.3400 3.3450 3.3500 3.3550 3.3600 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 v out [v] v in [v] io=1a io=2a io=3a figure 29. load transient: from 0.4 a to 3 a figure 30. soft-start v out 200mv/div ac coupled i l 1a/div time base 200us/div v in =24v v out =3.3v c out =47uf l=10uh f sw =520k i l 1a/div v out 1v/div time base 1ms/div i l 0.5a/div v out 0.5v/div time base 1ms/div i l 1a/div v out 1v/div time base 1ms/div i l 0.5a/div v out 0.5v/div time base 1ms/div figure 31. short-circuit behavior v in =12 v figure 32. short-circuit behavior v in =24 v out 5v/div i l 1a/div v out 1v/div synch 5v/div timebase 10us/div out 5v/div i l 1a/div v out 1v/div synch 5v/div timebase 10us/div out 5v/div i l 1a/div v out 1v/div synch 5v/div timebase 10us/div out 5v/div i l 1a/div v out 1v/div synch 5v/div out 5v/div i l 1a/div v out 1v/div synch 5v/div out 5v/div i l 1a/div v out 1v/div synch 5v/div timebase 10us/div
l7986ta application ideas doc id 022098 rev 3 35/43 7 application ideas 7.1 positive buck-boost the l7986ta can implement the step-up/down converter with a positive output voltage. figure 33. shows the schematic: one power mosfet and one schottky diode are added to the standard buck topology to provide 12 v output voltage with input voltage from 4.5 v to 38 v. figure 33. positive buck-boost regulator the relationship between input and output voltage is: equation 39 so the duty cycle is: equation 40 the output voltage isn?t limited by the maximum operating voltage of the device (38 v), because the output voltage is sensed only through the resistor divider. the external power mosfet maximum drain to source voltage must be higher than the output voltage; the maximum gate to source voltage must be higher than the input voltage (in figure 33 , if v in is higher than 16 v, the gate must be protected through a zener diode and resistor) the current flowing through the internal power mosfet is transferred to the load only during the off-time, so according to the maximum dc switch current (3.0 a), the maximum output current for the buck-boost topology can be calculated from the following equation. v out v in d 1d ? ------------- ? = d v out v out v in + ------------------------------- - =
application ideas l7986ta 36/43 doc id 022098 rev 3 equation 41 where i sw is the average current in the embedded power mosfet in the on-time. to choose the right value of the inductor and to manage transient output current, which for a short time can exceed the maximum output current calculated by equation 41 , also the peak current in the power mosfet must be calculated. the peak current, shown in equation 42 , must be lower than the minimum current limit (3.7 a). equation 42 where r is defined as the ratio between the inductor current ripple and the inductor dc current: so, in the buck-boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value). in figure 34 the maximum output current for the above configuration is depicted varying the input voltage from 4.5 v to 38 v. the dashed line considers a more accurate estimation of the duty cycles given by equation 43 , where power losses across diodes, external power mosfet, and internal power mosfet are taken into account. figure 34. maximum output current according to max. dc switch current (3.0 a): v o =12 v i sw i out 1d ? ------------- 3 a < = i sw,pk i out 1d ? ------------- 1 r 2 -- - + 3.7a < ? = r v out i out lf sw ?? ------------------------------------------- - 1d ? () 2 ? =
l7986ta application ideas doc id 022098 rev 3 37/43 equation 43 where v d is the voltage drop across the diodes, v sw and v swe across the internal and external power mosfet. 7.2 inverting buck-boost the l7986ta can implement the step-up/down converter with a negative output voltage. figure 33. shows the schematic to regulate -5 v: no further external components are added to the standard buck topology. the relationship between input and output voltage is: equation 44 so the duty cycle is: equation 45 as in the positive one, in the inverting buck-boost the current flowing through the power mosfet is transferred to the load only during the off-time. so according to the maximum dc switch current (3.0 a), the maximum output current can be calculated from equation 41 , where the duty cycle is given by equation 45 equation 45 . figure 35. inverting buck-boost regulator d v out 2v d ? + v in v sw v swe v out 2v ? d ++ ? ? --------------------------------------------------------------------------------------------------- = v out v in ? d 1d ? ------------- ? = d v out v out v in ? ------------------------------- - =
application ideas l7986ta 38/43 doc id 022098 rev 3 the gnd pin of the device is connected to the output voltage so, given the output voltage, input voltage range is limited by the maximum voltage the device can withstand across vcc and gnd (38 v). therefore, if the output is -5 v the input voltage can range from 4.5 v to 33 v. as in the positive buck-boost, the maximum output current according to application conditions is shown in figure 36 . the dashed line considers a more accurate estimation of the duty cycles given by equation 46 , where power losses across diodes and the internal power mosfet are taken into account. equation 46 figure 36. maximum output current according to switch max. peak current (3.0 a): v o =-5 v d v out v d ? v ? in v sw v out v d ? + ? -------------------------------------------------------------------- =
l7986ta package mechanical data doc id 022098 rev 3 39/43 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 10. hsop8 mechanical data dim mm min. typ. max. a 1.70 a1 0.00 0.150 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e1.27 h 0.25 0.50 l 0.40 1.27 k 0.00 8.00 ccc 0.10
package mechanical data l7986ta 40/43 doc id 022098 rev 3 figure 37. package dimensions $mm4yp %mm4yp !-v
l7986ta ordering information doc id 022098 rev 3 41/43 9 ordering information table 11. order code order code package packaging l7986ta hsop8 tube l7986tatr hsop8 tape and reel
revision history l7986ta 42/43 doc id 022098 rev 3 10 revision history table 12. document revision history date revision changes 25-oct-2011 1 initial release. 01-mar-2012 2 section 8: package mechanical data has been updated. 16-oct-2012 3 in section 5.6 changed temperature value from 130 to 120 c
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